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MOSEL VITELIC
MS7200L/7201AL/7202AL 256 x 9, 512 x 9, 1K x 9 CMOS FIFO
Descriptions
MS7200L/7201AL/7202AL
Features
s First-In/First-Out static RAM based dual port memory s Three densities in a x9 configuration s Low power versions s Includes empty, full, and half full status flags s Direct replacement for industry standard Mostek and IDT s Ultra high-speed 30 MHz FIFOs available with 33 ns cycle times. s Fully expandable in both depth and width s Simultaneous and asynchronous read and write s Auto retransmit capability s TTL compatible interface, single 5V 10% power supply s Available in 28 pin 300 mil and 600 mil plastic DIP, 32 Pin PLCC and 330 mil SOG
Pin Configurations
28-PIN PDIP
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23
VCC D4 D5 D6 D7 FL / RT RS EF
The MS7200L/7201AL/7202AL are dual-port static RAM based CMOS First-In/First-Out (FIFO) memories organized in nine-bit wide words. The devices are configured so that data is read out in the same sequential order that it was written in. Additional expansion logic is provided to allow for unlimited expansion of both word size and depth. The dual-port RAM array is internally sequenced by independent Read and Write pointers with no external addressing needed. Read and write operations are fully asynchronous and may occur simultaneously, even with the device operating at full speed. Status flags are provided for full, empty, and half-full conditions to eliminate data underflow and overflow. The x9 architecture provides an additional bit which may be used as a parity or control bit. In addition, the devices offer a retransmit capability which resets the Read pointer and allows for retransmission from the beginning of the data. The MS7200L/7201AL/7202AL are available in a range of frequencies from 10 to 30 MHz (33 - 100 ns cycle times). A low power version with a 500A power down supply current is available. They are manufactured on Mosel-Vitelic's high performance 1.2 CMOS process and operate from a single 5V power supply.
300 mil 600 mil DIP & 330 mil SOG
Block Diagram
DATA INPUTS (Q0-Q8)
22 21 20 19 18 17 16 15
XO / HF Q7 Q6 Q5 Q4 R
W
WRITE CONTROL
WRITE POINTER
RAM ARRAY 256x9 512x9 1Kx9
READ POINTER
32-PIN PLCC
VCC
THREE STATE BUFFERS DATA OUTPUTS (Q0-Q8)
29 28 27 26 25 24 23 22 21 D6 D7 NC FL / RT RS EF XO / HF Q7 Q6
W NC
D3
D8
D4
4 D2 D1 D0 XI FF Q0 Q1 NC Q2 5 8 7 8 9 10 11 14 13
3
2
1 32 31 30
D5
R
READ CONTROL RESET LOGIC FLAG LOGIC EF HF FF RS FL / RT
32 Pin PLCC Top View
14 15 16 17 18 19 20
VSS
XI
EXPANSION LOGIC
Q8
NC
R
Q4
Q3
Q5
XO
MS7200L/01AL/02AL Rev. 1.0 January 1995
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MOSEL VITELIC
Signal Descriptions
INPUTS: Data In (D 0 - D 8) These data inputs accept 9-bit data words for sequential storage in the FIFO during write operations. CONTROLS: Reset (RS) The reset input is active LOW. When asserted, the device is asynchronously reset, and both the read and write internal pointers are set to the first location in the FIFO. A Reset is required after power-up before a write operation can occur. Both Read Enable (R) and Write Enable (W) must be HIGH during Reset. Read Enable (R) The read enable input is active LOW. As long as the Empty Flag (EF) is not set, the read cycle is started on the falling edge of this signal. The data is accessed on a First-In/First-Out basis, independent of any write activity, and is presented on the Data Output pins (Q0 - Q8). When R goes HIGH the Data Output pins return to the high impedance state, and the read pointer is incremented. When the FIFO is empty or all of the data has been read, the Empty Flag will be set and further read operations are inhibited until a valid write operation has been performed. Write Enable (W) The write enable input is active LOW. As long as the Full Flag (FF) is not set, the write cycle is started on the falling edge of this signal. The data present on the Data Input pins (D0 - D8) is stored sequentially, independent of any read activity. When W goes HIGH the write cycle is terminated and the write pointer is incremented. When the maximum capacity of the FIFO has been reached the Full Flag will be set, and further write operations are inhibited until a valid read operation has been performed. Expansion In (XI) This input pin serves two purposes. When grounded, it indicates that the device is being operated in the single device mode. In Depth Expansion mode, this pin is connected to the Expansion Out Output (XO) of the previous device.
MS7200L/7201AL/7202AL
First Load/Retransmit (FL/RT) This is a dual-purpose input. In single device mode (when Expansion In (XI) is grounded) this pin acts as the retransmit input. A LOW pulse on this will reset the read pointer to the first memory location of the FIFO. The write pointer is unaffected. Both the read enable (R) and write enable (W) inputs must remain HIGH during the retransmit cycle. In Depth Expansion mode this pin acts as a first load indicator. It must be grounded on the first device in the chain to indicate which device is the first to receive data. OUTPUTS: Data Output (Q0 - Q 8) A 9 bit data word from the FIFO is output on these pins during read operations. They are in the high impedance state whenever R is HIGH. Empty Flag (EF) This output is active LOW. When all of the data has been read from the FIFO (defined as when the Read pointer is one location behind the Write pointer) this flag will be set. The Data Output pins will be forced into the high impedance state, and all further read operations will be inhibited until a valid write operation has been performed (which will reset this flag). Full Flag (FF) This output is active LOW. To prevent data overflow, when the maximum capacity of the FIFO has been reached (defined as when the Write pointer is one location behind the Read pointer) this flag will be set. All further write operations will be inhibited until a valid read operation has been performed (which will reset this flag). Expansion Out/Half Full Flag (XO/HF) This dual-purpose output is active LOW. In single device mode (when Expansion In (XI) is grounded) this flag will be set at the falling edge of the next write operation after the FIFO has reached one-half of its maximum capacity. This flag will remain set as long as the difference between the read pointer and the write pointer is greater than one-half of the maximum capacity of the FIFO. In Depth Expansion mode, this output is connected to the Expansion In Input of the next device in the chain. The Expansion Out pin provides a pulse to the next device in the chain when the last memory location has been reached.
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MS7200L/01AL/02AL Rev. 1.0 January 1995
MOSEL VITELIC
Absolute Maximum Ratings(1)
Symbol VTERM TBIAS TSTG PT IOUT 1. Parameter Terminal Voltage with Repect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Condition -0.5 to +7.0 -10 to +125 -60 to +150 1.0 20 Unit V C C W mA Range Commercial
MS7200L/7201AL/7202AL
Operating Range
Ambient Temperature 0C to + 70C Vcc 5V 10%
Capacitance(1) TA = 25C, f = 1.0MHz
Symbol C IN CQ Parameter Input Capacitance Output Capacitance Condition VIN = 0V VDQ = 0V Max. 4 6 Unit pF pF
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (over the commercial operating range)
Test Parameter V IL V IH I IL IOL V OL MS7200L/7201AL MS7200L/7201AL 7202AL 7202AL (-25, -35) (-50, -80) Min. Typ. Max. Min. Typ. Max. Units 2.0 -1 -10 2.4 0.8 1 10 0.4 125 15 2.0 -1 -10 2.4 0.8 1 10 0.4 80 8 V V A A V V mA mA
Parameter Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage
Test Conditions
V CC = Max, V IN = 0Vto V CC V CC = Max, R= VIH, VIN = 0V toVCC V CC = Min, IOL = 8mA V CC = Min, IOH = -2mA
-
50 5
VOH ICC1
ICC2
ICCSB(S)
ICCSB(L)
Operating Power Supply Current V CC = Max, II/O = 0mA, F = Fm ax V CC = Max, R = W = RS = FL / RT = Average Standby Current V IH, I I/O = 0mA V CC = Max, R = W = RS = FL / RT > Power Down Power Supply V CC-0.2V, V IN > V CC-0.2V or V IN < Current (Standard Power) 0.2V V CC = Max, R = W = RS = FL / RT > Power Down Power Supply V CC-0.2V, V IN > V CC-0.2V or V IN < Current (Low Power) 0.2V
-
-
5
-
-
5
mA
-
-
500
-
-
500
A
Truth Tables
Single Device Configuration/Width Expansion Mode
Mode RS Reset Retransmit 0 1 Inputs RT X 0 XI 0 0 0 Internal Status Read Pointer Location Zero Location Zero Increment (1) Write Pointer Location Zero Unchanged Increment (1) EF 0 X X Outputs FF 1 X X HF 1 X X
Read/Write 1 1 NOTE: 1. Pointer will increment if flag is high.
Depth Expansion/Compound Expansion Mode
Mode RS Reset-First Device Reset all Other Devices 0 0 Inputs FL 0 1 XI (1) (1) Internal Status Read Pointer Location Zero Location Zero Write Pointer Location Zero Unchanged EF 0 0 Outputs FF 1 1
Read/Write 1 X (1) X X X X NOTE: 1. XI is connected to XO of previous device. See Figure 15. RS = Reset Input. FL/RT = First Load/Retransmit. EF = Empty Flag Output. FF Full Flag Output. XI = Expansion Input.
MS7200L/01AL/02AL Rev. 1.0 January 1995
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MOSEL VITELIC
MS7200L/7201AL/7202AL
MS7200L-25 MS7200L-35 MS7200L-50 MS7200L-80 MS7201AL-25 MS7201AL-35 MS7201AL-50 MS7201AL-80 MS7202AL-25 MS7202AL-35 MS7202AL-50 MS7202AL-80 Min. Max. Min. Max. Min. Max. Min. Max. -30 -22.2 -15 -10 33 -25 8 5 -5 33 25 8 15 0 5 ------25 25 33 25 25 8 ---33 25 25 8 --25 15 8 -25 ---18 -------25 33 25 25 25 33 ------33 33 33 ----25 25 ---45 -35 10 5 -5 45 35 10 18 0 10 ------35 35 45 35 35 10 ---45 35 35 10 --35 15 10 -35 ---20 -------30 45 30 30 30 45 ------45 45 45 ----35 35 ---65 -50 15 10 -5 65 50 15 30 5 15 ------50 50 65 50 50 15 ---65 50 50 15 --50 15 10 -50 ---30 -------45 65 45 45 45 65 ------65 65 65 ----50 50 ---100 -80 20 10 -5 100 80 20 40 10 20 ------80 80 100 80 80 20 ---100 80 80 20 --80 15 10 -80 ---30 -------60 100 60 60 60 100 ------100 100 100 ----80 80 ----
AC Electrical Characteristics (over the commercial operating range)
Parameter Name Parameter S Shift Frequency Read Cycle tRC Read Cycle Time tA Access Time tRPW Read Pulse Width tRR Read Recovery Time tRLZ (2) Read Pulse Low to Data Bus at Low Z tRHZ (2,3) Read Pulse High to Data Bus at High Z tDV Data Valid from Read Pulse High Write Cycle tWC Write Cycle Time tWPW(1) Write Pulse Width tWR Write Recovery Time tDS Data Setup Time tDH Data Hold Time tWLZ(2,3) Write Pulse High to Data Bus at Low Z Flag Timing tREF Read Low to Empty Flag Low tRHF Read High to Half Full Flag High tRFF Read High to Full Flag High tWEF Write High to Empty Flag High tWFF Write Low to Full Flag Low tWHF Write Low to Half Full Flag Low tRPE Read Pulse Width After EF High tWPF Write Pulse Width After FF High Reset Timing tRSC Reset Cycle Time tRS (1) Reset Pulse Width tRSS Reset Set Up Time tRSR Reset Recovery Time tEFL Reset to Empty Flag Low tHFH Reset to Half Full Flag High tFFH Reset to Full Flag High Retransmit Timing tRTC Retransmit Cycle Time tRT(1) Retransmit Pulse Width tRTS Retransmit Set up Time tRTR Retransmit Recovery Time Expansion Timing tXOL Read/Write to XO Low tXOH Read/Write to XO High tXI XI Pulse Width tXIS XI Set up Time tXIR XI Recovery Time
Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Pulse widths less than minimum value are not allowed. 2. Values guaranteed by design, not currently tested. 3. Only applies to read data flow-through mode.
MS7200L/01AL/02AL Rev. 1.0 January 1995
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MOSEL VITELIC
AC Test Conditions
Input Pulse Levels Input Rise and Fall Times Timing Reference Level 0V~ 3.0V 5 ns 1.5V
MS7200L/7201AL/7202AL
Key to Switching Waveforms
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L R1 480 5V OUTPUT MAY CHANGE FROM L TO H 5pF INCLUDING JIG AND SCOPE Figure 1b THEVENIN EQUIVALENT 167 OUTPUT ALL INPUT PULSES 1.73V R2 255 WILL BE CHANGING FROM L TO H CHANGING: STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF" STATE OUTPUTS WILL BE STEADY WILL BE CHANGING FROM H TO L
AC Test Loads and Waveforms
R1 480 5V OUTPUT 30pF INCLUDING JIG AND SCOPE Figure 1a Equivalent to: R2 255
DON'T CARE: ANY CHANGE PERMITTED
DOES NOT APPLY
3.0V GND 5 ns
90% 10%
90% 10% 5 ns
Figure 2
Timing Waveforms
RESET
RS t RS t RSC
t RSS W
t EFL EF
t RSR
HF, FF
t HFH , t FFH
t RSS R
ASYNCHRONOUS READ OPERATION
t RC t RR R tA tA t RPW
t RLZ Q0-Q8
t DV READ DATA VALID
t RHZ READ DATA VALID
MS7200L/01AL/02AL Rev. 1.0 January 1995
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MOSEL VITELIC
Timing Waveforms
ASYNCHRONOUS WRITE OPERATION
MS7200L/7201AL/7202AL
t WC t WPW W t WR
t DS D0-D8
t DH WRITE DATA VALID
WRITE DATA VALID
RETRANSMIT
t RTC FL / RT t RT
t RTS R, W t RTR
EMPTY FLAG TIMING
W t WEF EF t RPE R t RPE: EFFECTIVE READ PULSE WIDTH AFTER EMPTY FLAG HIGH
MS7200L/01AL/02AL Rev. 1.0 January 1995
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MOSEL VITELIC
Timing Waveforms
FULL FLAG TIMING
MS7200L/7201AL/7202AL
R t RFF FF t WPF W t WPF : EFFECTIVE WRITE PULSE WIDTH AFTER FULL FLAG HIGH
HALF-FULL FLAG TIMING
HALF-FULL OR LESS W
MORE THAN HALF-FULL
HALF-FULL OR LESS
R HF t WHF
t RHF
FULL FLAG FROM LAST WRITE TO FIRST READ
LAST WRITE R
FIRST READ
ADDITIONAL FIRST WRITE READS
W
t WFF FF
tRFF
MS7200L/01AL/02AL Rev. 1.0 January 1995
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MOSEL VITELIC
Timing Waveforms
EMPTY FLAG FROM LAST READ TO FIRST WRITE
LAST READ W FIRST WRITE ADDITIONAL WRITES
MS7200L/7201AL/7202AL
FIRST READ
R t REF EF tWEF
tA DATA OUT
VALID VALID
READ DATA FLOW-THROUGH MODE
DATA IN
W tRPE R
EF tWLZ DATA OUT
tWEF
tREF tA
DATA OUT VALID
WRITE DATA FLOW-THROUGH MODE
R tWPF W tRFF FF t WFF tDH DATA IN tA DATA OUT
MS7200L/01AL/02AL Rev. 1.0 January 1995
DATA OUT VALID DATA IN VALID
tDS
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MOSEL VITELIC
Timing Waveforms
EXPANSION IN
MS7200L/7201AL/7202AL
t XI XI t XIS W
t XIR
WRITE TO FIRST PHYSICAL LOCATION t XIS READ FROM FIRST PHYSICAL LOCATION
R
EXPANSION OUT
W
WRITE TO LAST PHYSICAL LOCATION READ FROM LAST PHYSICAL LOCATION t XOL t XOH t XOL t XOH
R
XO
Operating Modes:
(Note: The7201A Lis used as example - these figures apply to all three devices, MS7200L/ 7201AL/7202AL
HALF FULL FLAG (HF)
Single Device Mode
When one MS7201AL is used standalone in Single Device Mode, the Expansion In (XI) control input pin must be grounded. See Figure 3.
(W)
WRITE
READ
(R)
(D0-D8)
DATA IN MS 7201A
DATA OUT
(Q0-Q8)
(FF)
FULL FLAG
EMPTY FLAG
(EF)
(RS)
RESET
RETRANSMIT
(RT)
EXPANSION IN XI
Figure 3. Single Device Mode
MS7200L/01AL/02AL Rev. 1.0 January 1995
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MOSEL VITELIC
Width Expansion Mode
Word width may be expanded by connecting the corresponding control input signals of multiple devices together. The EMPTY, HALF FULL and FULL FLAGS (EE, HF and FF) can be detected by
MS7200L/7201AL/7202AL
any particular device. Figure 4 shows an 18 bit wide configuration using two devices. They may be configured to any word width in this manner.
HALF FULL FLAG (HF)
9 DATA IN (D) 9 18 (W) (FF) (RS) RESET 18 MS 7201A 9 DATA OUT XI XI 9 (Q) WRITE FULL FLAG BITS 0-8 READ BITS 9-17 EMPTY FLAG (R) (EF) (HF) HALF FULL FLAG MS 7201A
RETRANSMIT
(RT)
Figure 4. Width Expansion Mode NOTES: Flag detection is accomplished by monitoring the EF, HF and EF pins on the device used in the Width Expansion Mode. Do not connect output control signals together.
Depth Expansion (Daisy Chain) Mode
Word depths may be expanded in multiples of 512 words by Daisy Chaining the devices together as follows: 1. The FIRST LOAD (FL) control signal of the first device must be grounded. This FIFO represents word 1-512. 2. All other devices in the Daisy Chain must have the FIRST LOAD (FL) control signal tied to VCC in the inactive-high state.
3. The EXPANSION OUT (XO) pin of each device must be connected to the EXPANSION IN (XI) pin of the next device as shown in Figure 5. 4. External logic is required to generate a common FULL FLAG (FF) and EMPTY FLAG (EF) signal by ORing all of the FFs together and ORing all of the EFs together. 5. The RETRANSMIT (RT) fuction and HALF FULL FLAG (HF) are not available in Daisy Chain Mode.
XO
W FF 9 D 9
MS 7201 WORDS 10251536 XI XO
EF 9 Q FL
R
VCC
FF FULL 9
MS 7201 WORDS 15131024 XI XO
EF EMPTY
FL
FF 9
MS 7201 WORDS 1-512
EF
RS XI
FL
Figure 5. Diagram of a 1536 x 9 FIFO in Depth Expansion Mode
MS7200L/01AL/02AL Rev. 1.0 January 1995
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MOSEL VITELIC
Bidirectional Mode
Data buffering between two systems can be achieved by pairing two FIFO arrays as shown in Figure 6. This allows each system to READ and WRITE shared data. The FULL FLAG (FF) must be monitored on the FIFO where WRITE ENABLE (W) is used and the EMPTY FLAG (EF) must be monitored on the FIFO where READ ENABLE (R) is used. Both Width Expansion and Depth Expansion
MS7200L/7201AL/7202AL
Modes may be used in combination with Bidirectional Mode.
Compound Expansion Mode:
Both Width Expansion Mode and Depth Expansion (Daisy Chain) Mode can be used together to configure a large FIFO array (See Figure 4 and 5).
WA FFA MS7201 DA 0-8 QB 0-8
RB EFB HFB
SYSTEM A
SYSTEM B
QA 0-8 RA EFA HFA
MS7201
DB WB FFB
Figure 6. BiDirectional FIFO Mode
Ordering Information
Speed (ns) 25 25 25 25 35 35 35 35 50 50 50 50 80 80 80 80 Ordering Part Number MS7201AL-25PC MS7202AL-25PC MS7200-25NC MS7201AL-25NC MS7202AL-25NC MS7200-25JC MS7201AL-25JC MS7202AL-25JC MS7200-25FC MS7201AL-25FC MS7202AL-25FC MS7201AL-35PC MS7202AL-35PC MS7200-35NC MS7201AL-35NC MS7202AL-35NC MS7200-35JC MS7201AL-35JC MS7202AL-35JC MS7200-35FC MS7201AL-35FC MS7202AL-35FC MS7201AL-50PC MS7202AL-50PC MS7200-50NC MS7201AL-50NC MS7202AL-50NC MS7200-50JC MS7201AL-50JC MS7202AL-50JC MS7200-50FC MS7201AL-50FC MS7202AL-50FC MS7201AL-80PC MS7202AL-80PC MS7200-80NC MS7201AL-80NC MS7202AL-80NC MS7200-80JC MS7201AL-80JC MS7202AL-80JC MS7200-80FC MS7201AL-80FC MS7202AL-80FC Package 28 Pin Plastic DIP - 600 mil 28 Pin Plastic DIP - 300 mil 32 Pin Plastic PLCC 28 Pin Small Outline - 330 mil 28 Pin Plastic DIP - 600 mil 28 Pin Plastic DIP - 300 mil 32 Pin Plastic PLCC 28 Pin Small Outline - 330 mil 28 Pin Plastic DIP - 600 mil 28 Pin Plastic DIP - 300 mil 32 Pin Plastic PLCC 28 Pin Small Outline - 330 mil 28 Pin Plastic DIP - 600 mil 28 Pin Plastic DIP - 300 mil 32 Pin Plastic PLCC 28 Pin Small Outline - 330 mil Temperature Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C
MS7200L/01AL/02AL Rev. 1.0 January 1995
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